1. Field of the Invention
The present invention relates to a multiprocessor system and address solution method thereof, more particularly to a multiprocessor system having distributed shared memory type architecture and its address solution method.
2. Description of the Related Art
A distributed shared memory architecture where memories are distributed and arranged in the vicinity of processors has a feature in which an access to a local memory is made at high speed as compared with a system in which all memories are intensively arranged. On the other hand, in the case where the memories placed at the different physical positions are set in a single memory space in the distributed shared memory constitution, determination is made as to whether a memory access is to a local memory access or to a remote memory access. If it is to the remote memory, the need for transfer arises. For this reason, some means for solving the address (for example, an address conversion table) is needed.
Moreover, in the system of the typical distributed shared memory constitution, a method for constituting a large scale system is often adopted in which a plurality of constitutional units (hereinafter referred to as a cell) including a processor, a memory and other computer primary constitutional components is packaged and these cells are interconnected by a network. In this case, implementation in which the respective cells are separated and each cell is operated as an independent computer can be relatively easily made. Such a separation is called partitioning, and the separated cell in this case is particularly referred to as a partition. If such a constitution is accepted, it brings about improvements in which a large-scale system can be easily implemented as compared with the intensive memory type system.
On the other hand, in a computer of a large-scale symmetric multiprocessor in which the memories are shared by the large number of processors, there is difficulty in increasing performance (improvement of scalability) in proportion to the number of processors because of limitation on software and competition for resources. Also, there is a physical limitation in increasing the number of processors. For this reason, there is a case where means for interconnecting a plurality of computers to implement large-scale processing ability is adopted. Such a system is called a cluster system. Each independent computer is particularly referred to as a node. The cluster system brings about not only a breakthrough of the limitation of system scale but also the availability. Namely, the plurality of computers is independently operated so as to prevent trouble and crush occurred at one portion from extending through the entire system. For this reason, the cluster system is often used to implement a system of high reliability.
However, the above-described cluster system has problems that setup and management become complicated and additional cost relating to the housing and interconnection cable is required. For this reason, there has come on the market the so-called inner housing cluster system where a plurality of small sized computers is put into one housing and necessary interconnection is made in the housing, and setup and testing are finished before shipment. However, in the existing cluster system including the above product, since a network is used to interconnect the computers, the communication overhead becomes large and there has been difficulty in improving performance in proportion to an increase in the number of nodes.
On the other hand, in the large-scale single computer system, there is a case where effect of improvement in performance cannot be easily obtained depending on the content of processing even if the number of processors is increased. Additionally, there has been a problem where a single failure and trouble easily extended through the entire system.
To solve the above problems, in Japanese published unexamined Patent Application No. 10-166723, as shown in FIG. 17, an address solution table is provided in each cell controlling circuit, so that the distributed shared system can be operated as a symmetric type multiprocessor and one system can be operated as a cluster system. This makes it possible to operate the same distributed shared memory architecture system selectively as a single symmetric shared memory computer and an inner housing cluster system.
However, in the above prior art, it is necessary to package address solution tables into all cells to be loaded, and there is a problem that the cell, which has no address solution table for the cluster function packaged thereon, cannot be loaded in the case of using the cluster constitution.
Additionally, since each cell is an independent computer and at the same time a node constitutional component, an input/output controlling apparatus is also loaded on the cell as shown in FIG. 18. Therefore, since the number of input/output controlling apparatuses, which is mounted on the cell constituting the node, is the upper limit of the number of input/output controlling apparatuses belonging to each node, there is a problem in which the performance of input/output processing cannot be implemented more than the number of input/output controlling apparatuses in one node. In this case, even if the input/output controlling apparatus is provided to the outer portion of cell, the cluster constitution cannot be obtained unless the address solution table is packaged in the input/output controlling apparatus itself.
Moreover, for example, as shown in FIG. 15, in the constitution where the cell has the input/output controlling apparatus, if a problem occurs in a cell of a certain node during the operation of cluster constitution, separating the cell produces the effect that the input/output controlling apparatus cannot be used even if the input/output controlling apparatus is normal.
The object of the present invention is to enable a cell, which has no address solution table for cluster function mounted thereon, to be operated as a node structural component and the same distributed shared memory architecture system can be selectively operated as a single symmetric multiprocessor computer or as an inner housing cluster system. By this operation, without depending on the function of a cell, a flexible computer system can be provided where the problems of both systems are solved according to the content of processing and the advantages of each system can be obtained.
Moreover, the object of the present invention is to make an operation as a cluster system possible even if the input/output controlling apparatus, which has no address solution table thereon, is connected thereto, and to perform assignment of the connected input/output controlling apparatus to each node flexibly.
In order to solve the above problems, the present invention provides a multiprocessor system, which is constituted by connecting a plurality of cells, comprises a network, at least one processor and a memory, wherein the network determines which memory of a cell an address specified by one of the plurality of cells indicates.